The present invention relates to a method for forming contact holes for metal interconnections in semiconductor devices and, more particularly, to a method for removing a polysilicon pattern used as a hard mask for forming contact holes without also removing a portion of the semiconductor substrate in the contact region.
In a semiconductor device manufacturing process, an etching process for forming contact holes is essential for connecting unit devices. In forming the contact holes, it is especially important that the selective etching rate be appropriate in order to clear the metal contact holes without damaging underlying structures.
In a dynamic random access memory (DRAM), the main elements include a gate electrode, a bit line, a plate electrode and an active region. The upper layer of the gate electrode and the bit line are typically formed using a tungsten silicide layer and the capacitor plate electrode is typically formed using an amorphous silicon layer. The active region is, in turn, typically formed in an implanted single crystal silicon substrate.
FIG. 1 is a cross-sectional view illustrating a conventional method for forming contact holes for metal interconnection in semiconductor devices. In this method, a gate insulation layer 11 is formed on a semiconductor substrate 10. A gate electrode 12 is then formed on the gate insulation layer 11. An interlayer insulation layer 14 and a polysilicon layer 16 are then sequentially formed on the resulting structure. A photoresist pattern 18 is then formed on the polysilicon layer 16 in order to expose those areas in which metal interconnection contact holes will be formed through the interlayer insulation layer to the semiconductor substrate 10.
After forming the photoresist pattern 18, the polysilicon layer 16, the interlayer insulation layer 14 and the gate insulation layer 11 are etched to open a metal interconnection contact hole 19 using the photoresist pattern 18 as an initial etching mask and the polysilicon layer 16 as a hard etch mask. In this process, however, when the photoresist pattern 18 and the polysilicon layer 16 are subsequently removed, a portion of the semiconductor substrate 10 exposed at the bottom of the metal interconnection contact hole 19 may also be removed.
As described above, in the conventional method of forming contact holes for metal interconnection in semiconductor devices, the thick interlayer insulation layer 14 provides an etch processing margin over the hard mask formed from polysilicon layer 16. After the metal interconnection contact hole 19 has been formed, the photoresist pattern 18 and the polysilicon layer 16 are removed.
However, the portion of the semiconductor substrate which is exposed at the bottom of the metal interconnection contact hole 19 will be removed at approximately the same rate as the polysilicon layer 16. Accordingly, this lack of selectivity results in the removal of some of the semiconductor substrate during the etching process used to remove the polysilicon layer 16.
It is, therefore, an object of the present invention to provide a method for forming contact holes for metal interconnection in semiconductor devices that prevents the loss of semiconductor substrate in the contact area.
In the present invention, after forming a gate electrode, a nitride layer, which has a lower etching rate than both the interlayer insulation layer and the polysilicon layer, is formed on the resulting structure. This nitride layer acts to prevent the loss of the semiconductor substrate from the bottom of the contact holes by the etch used after the contact etch to remove the polysilicon layer. As a result, the present invention improves the operational characteristics and increases the yield of the resulting semiconductor devices.
In accordance with an aspect of the present invention, there is provided a method for forming metal interconnection contact holes for semiconductor devices comprising the steps of: forming a nitride layer on a contact region to be contacted with a conducting layer; forming an interlayer insulation layer on the nitride layer, wherein the interlayer insulation layer has a different and higher etching rate than the nitride layer, the nitride layer acting as an etching barrier layer during the interlayer insulation layer etch; forming a polysilicon layer on the interlayer insulation layer; etching the polysilicon layer to form a polysilicon pattern as a hard mask; etching the interlayer insulation layer using the polysilicon pattern as an etching mask, thereby forming a first opening that exposes a portion of the nitride layer; and etching the exposed nitride layer, thereby forming a second opening and exposing the contact region.